1. Field of the Invention
The present invention relates to an image display device, and more particularly, to an image display device capable of displaying an expanded image signal when an image signal input to the device has a smaller number of pixels than the number of pixels of a display panel.
The present invention also relates to a driver circuit for use in a display device with a high-resolution display panel in which the resolution is switched during an operation.
2. Description of the Related Art
In image display devices for use in personal computers or the like, the number of pixels of a display panel is defined in various standards. Widely used standards include VGA, SGVA, XGA, SXGA, and UXGA. In these standards, the number of pixels per frame is defined as follows.
VGA: 640 pixels in the horizontal direction and 480 pixels in the vertical direction;
SVGA: 800 pixels in the horizontal direction and 600 pixels in the vertical direction;
XGA: 1024 pixels in the horizontal direction and 768 pixels in the vertical direction;
SXGA: 1280 pixels in the horizontal direction and 1024 pixels in the vertical direction; and
UXGA: 1600 pixels in the horizontal direction and 1200 pixels in the vertical direction.
(In the above description, VGA, SVGA, XGA, SXGA, and UXGA are all registered trademarks of IBM Corp.)
In some cases, it is required to display an image signal on a display device according to a standard which is different from that of the image signal such as when a VGA image signal is displayed on an XGA display panel. In such a case, it is required to expand a VGA image signal to a size corresponding to the size of the XGA high-resolution display panel.
Two conventional signal expansion techniques are known in the art of the image display device as described below.
A first technique is, as shown in FIG. 8, to switch the sampling frequency at which an analog-to-digital converter 101 converts an analog signal to a digital signal.
For example, when an analog signal such as that shown on the top of FIG. 9 is given, if the analog signal is sampled in response to a clock signal 1 at a fixed frequency, then digital data 1 is obtained as denoted by A, B, C, D, E, F, G, . . . If the same analog signal is sampled in response to a clock signal 2 at a higher frequency, then different digital data 2 is obtained as denoted by h, i, j, k, l, m, n, o, p, q, r, . . . The latter digital data 2 includes an increased number of data compared to the digital data 1 obtained using the clock 1. This means that the image signal is expanded.
The second technique is to detect the resolution of a given image signal and to set the expansion ratio to a value corresponding to the ratio of the resolution of the display panel to that of the given image. Each frame of image signal is expanded according to the above expansion ratio by means of interpolation using an arithmetic circuit.
For example, when a VGA image signal is converted to an XGA image signal, the required expansion ratio is 1.6. This expansion ratio may be achieved for example by converting five data to eight data. More specifically, eight data h, i, j, k, 1, m, n, and o are produced by means of calculation from five original data A, B, C, D, and E as shown ion FIG. 10. The calculation may be performed using the following equations: EQU h=A.times.1.0 for data h, EQU i=A.times.0.3+B.times.0.2 for data i, EQU j=B.times.1.0 for data j, EQU k=B.times.0.1+C.times.0.4 for data k, EQU l=C.times.0.4+D.times.0.1 for data l, EQU m=D.times.1.0 for data m for data m,
n=D.times.0.2+E.times.0.3 for data n,
and EQU o=E.times.1.0 for data o.
In the standards described above, each pixel usually consists of three dots representing red (R), blue (B), and green (G), respectively.
When images according to various standards are modified so as to fit them to the display panel, it is required to expand or reduce the image including characters or the like such that the expanded or reduced image is displayed over the fixed display area of the screen.
The following signal expansion techniques are known in the art of the display device.
In one technique, the resolution of given image data is detected using a detection circuit and an expansion ratio is set depending on the ratio of the resolution of the display panel to the detected resolution of the image data. One frame of image data is stored in a frame memory and two consecutive lines of image data are read at a time from the frame memory. The two lines of image are expanded according to the above expansion ratio by means of interpolation using an arithmetic circuit, and resultant image is displayed on the display panel.
In the structure in which pixels each consisting of three dots are arranged in a matrix fashion, original luminance data to be displayed on three dots in each line are expanded using the arithmetic circuit wherein luminance is weighted by predetermined factors. The resultant expanded luminance data is applied to dots of respective pixels so that an image expanded in the direction along the line is displayed on the display panel.
In the above-described techniques, data calculation and re-sampling are required. Besides, an additional memory is required. As a result, the circuit becomes greater in scale and thus it becomes difficult to achieve a small-sized display device and higher cost is required.
One technique of displaying an expanded image without using an additional memory is to employ a display device constructed as shown in FIG. 26, which will be further improved according to the present invention as will be described later.
The display device shown in FIG. 26 includes a thin-film transistor liquid crystal display panel 201 including source interconnection lines and gate interconnection lines extending in a matrix fashion, first horizontal driver 202 and a second horizontal driver 203 connected to the source interconnection lines of the display panel 201, a vertical driver 204 connected to the gate interconnection lines of the display panel 201, and a signal processing circuit 205 for controlling the drivers 202, 203, and 204.
The signal processing circuit 205 includes a sampling circuit 207 to which an image signal or an original data is input, a frequency divider 208 and a signal selection circuit 209 both connected to the sampling circuit 207, a horizontal control circuit 210 for controlling the horizontal drivers 202 and 203, and a vertical control circuit 211 for controlling the vertical driver 204. A clock generator 212 is connected to the signal processing circuit 205. The liquid crystal display panel 201 employed herein is assumed to be of the XGA type including 1024 pixels in the horizontal direction and 768 pixels in the vertical direction.
In the display device shown in FIG. 26, if original data or an image signal according to the VGA standard (at a clock frequency of 27.175 MHz) such as a signal H (ABCDE . . . ) shown in FIG. 27 is input to the signal processing circuit 205, the signal is input to the sampling circuit 207. In synchronization with a sampling clock signal at 40.28 MHz, the sampling circuit 207 produces converted data I (AABCCDEE . . . ) as shown in FIG. 27. The resultant converted data I is sent to the frequency divider 208. In the above operation, in order to convert the VGA image signal with 1H=640 data to an XGA signal with 1H=1024 data, it is required to increase the number of data by a factor of 1.6 and thus the sampling is performed at a sampling clock frequency of 40.28 MHz which is 1.6 times the original clock frequency of 27.175 MHz.
After that, the converted data is divided by the frequency divider 208 into odd-numbered signals and even-numbered signals. The odd-numbered signals ABCE, . . . , which are represented by J in FIG. 27, are supplied via the signal selection circuit 209 to the first horizontal drier 202. Similarly, the even-numbered signals ACDE, . . . , which are represented by K in FIG. 27, are supplied to the second horizontal driver 203.
The horizontal control circuit 210 controls the drivers 202 and 203 so that signals are supplied to the source interconnection lines of the liquid crystal display panel 201 alternately from the first horizontal driver 202 and the second horizontal driver 203 thereby allowing the liquid crystal display panel 201 designed to display XGA images to display data AABCCDEE . . . as shown in FIG. 27 (data L) and also as shown on the liquid crystal panel 201 in FIG. 26.
On the other hand, in the case where XGA image signal is input as original data, the image signal is directly sent to the frequency divider 208 as represented by I' in FIG. 26 without being passed through the sampling circuit 207, and is subjected to the same dividing process in the frequency divider 208 as that described above. The XGA image signal is divided by the signal selection circuit 209 into two parts and supplied to the liquid crystal display panel 201. The divided signals are combined together on the display panel 201, and thus an XGA image is displayed thereon.
As described above, by employing the circuit shown in FIG. 26, it is possible to convert an original VGA image signal to XGA image signal by means of re-sampling the original image signal. The resultant XGA image signal is supplied to the liquid crystal display panel 201 and thus an XGA image originated from the VGA image signal is displayed on the liquid crystal display device 201.
However, the both signal expanding techniques described above have their own problems.
In the first technique, when an image signal generated by a personal computer is input as original data, miss-sampling can occur due to the difference from an ordinary image signal. The miss-sampling can cause flicker which results in degradation in image quality. Another problem is that when sampling is not performed at maximum and minimum values of the waveform of a given analog signal, a reduction in contrast occurs.
The problem of the second technique is that original data is not perfectly preserved after conversion and degradation in image quality such as a reduction in contrast can occur. In the specific example shown in FIG. 10, four data A, B, D, and E of the original data A, B, C, D, and E are converted by multiplying them by a factor of 1.0 and thus these data are directly employed as the converted data h, j, m, and o, respectively. However, the original data C is dispersed into components of the converted data k and l, and thus the data C is not preserved in its original form after the conversion. Therefore, although the overall converted image will be similar to the original image, a loss can occur in some individual data as is the case for data C in this specific example. Such a loss of data can cause a reduction in contrast.
The circuit configuration shown in FIG. 26 requires an additional circuit for generating a clock signal at a frequency different from that of original data. This result in an increase in the scale of the circuit which makes it difficult to achieve a small-sized display device. Furthermore, the operation at a higher frequency results in an increase in power consumption. For example, if a signal processing circuit which needs power consumption of 250 mw at a normal frequency is operated at a higher frequency, the power consumption will increase to about 400 mW. Furthermore, in the sampling operation on digital data at a different frequency, it is needed to meet severe requirements in terms of the sampling setup time and hold time. These severe requirements can cause degradation in reliability of the display device and also degradation in image quality.